Huawei has fundamentally altered the trajectory of the global artificial intelligence semiconductor race. At its annual Huawei Connect event in Shanghai, the Chinese technology conglomerate publicly disclosed a dramatically accelerated roadmap for its Ascend series of AI processors, signaling an open and ambitious challenge to Nvidia’s longstanding dominance in the AI accelerator market. This disclosure represents a significant departure from Huawei’s historically secretive approach to its chip development progress, reflecting both growing confidence and the urgent demands of an AI industry that consumes computing power at an unprecedented rate.
The centerpiece of Huawei’s announcement was the confirmation that its next-generation Ascend 960DT processor will arrive in the first quarter of 2027, a full three quarters ahead of the company’s previously stated roadmap. This acceleration, driven by the company’s proprietary Tau Scaling Law methodology, sets the stage for a relentless annual cadence of chip releases that will see the Ascend 970 debut in 2028 and the Ascend 980 in 2029. The implications of this roadmap extend far beyond Huawei itself, touching every facet of the global AI infrastructure landscape, from data center operators to cloud service providers and the enterprises that depend on them.
Understanding the Tau Scaling Law and Huawei’s Design Philosophy
The strategic acceleration of Huawei’s chip roadmap is not merely a matter of resource allocation or manufacturing efficiency. It is rooted in a fundamental design philosophy that the company calls the Tau (τ) Scaling Law. This proprietary framework guides the architectural evolution of the Ascend series, ensuring that each successive generation delivers not just incremental improvements but transformative leaps in compute density, memory bandwidth, and interconnect performance.
The Tau Scaling Law represents Huawei’s answer to the physical limitations imposed by advanced semiconductor manufacturing constraints. Rather than pursuing ever-smaller transistor geometries, a path that has been effectively blocked by export controls on extreme ultraviolet lithography equipment, Huawei has chosen to focus on architectural innovation, advanced packaging, and system-level integration. The LogicFolding design approach, unveiled by Huawei’s semiconductor chief He Tingbo, exemplifies this strategy by targeting 1.4-nanometer-equivalent chip performance by 2031 through advanced stacking technology.
The results of this design philosophy are already visible in the Ascend 960DT specifications. The chip will feature a new SIMD/SIMT architecture capable of supporting an extensive range of data formats, including FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, and HiF4. These “H” formats, which account for both precision and dynamic range, enable the consolidation of two standard floating-point formats into a single, more efficient representation. The Ascend 960DT will deliver up to 2 PFLOPs of FP8 compute and 4 PFLOPs of FP4 compute, alongside 288 GB of HBM operating at 9.6 TB/s, representing a 2.4x increase over the Ascend 950 series.
The Ascend Chip Portfolio: A Generation-by-Generation Breakdown
Huawei’s expanded Ascend portfolio encompasses multiple distinct chip variants, each optimized for specific workloads and deployment scenarios. Understanding the capabilities of each processor provides insight into Huawei’s strategic vision for the AI infrastructure market.
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Ascend 960DT (Q1 2027): The flagship of the 960 generation, this processor is designed for both training and inference workloads. It features 288 GB of HBM at 9.6 TB/s bandwidth, 2.2 TB/s of interconnect bandwidth, and delivers 2 PFLOPs of FP8 or 4 PFLOPs of FP4 compute.
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Ascend 960PR (Q3 2027): Optimized specifically for inference tasks, the 960PR trades memory capacity for raw throughput, featuring a leaner 192 GB of HBM at 2.4 TB/s and an impressive 8 PFLOPs of FP4 compute.
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Ascend 970 (2028): This generation introduces a major architectural uplift with up to 3.6 PFLOPs of FP8 and 14 PFLOPs of FP4 compute. It features 288 GB of HBM operating at 14.4 TB/s, pointing to a new HBM standard, along with 4.4 TB/s of interconnect bandwidth.
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Ascend 980 (2029): The most ambitious chip in the current roadmap, the 980 will boost compute to 7.2 PFLOPs in FP8 and 28 PFLOPs in FP4. It will feature 384 GB of HBM at 38.4 TB/s of bandwidth and 8 TB/s of interconnect bandwidth, though Huawei notes these specifications are preliminary and may evolve.
This systematic progression reflects Huawei’s commitment to maintaining a one-generation-per-year update cycle, a cadence that, if sustained, will position the company as a persistent and increasingly capable competitor in the global AI accelerator market.
The Atlas 960E SuperPoD: System-Level Innovation
While individual chip performance captures headlines, Huawei’s true competitive advantage may lie in its system-level approach to AI infrastructure. The Atlas 960E SuperPoD, announced alongside the Ascend 960 chips, represents the industry’s first SuperPoD to utilize near-packaged optics technology. This system-level innovation allows Huawei to compensate for per-chip performance gaps with massive scale and efficient interconnect.
A single Atlas 960E SuperPoD houses 4,096 NPUs and delivers 8 EFLOPS of FP8 compute performance, with memory scaling to a full petabyte of HBM capacity. The optical engine at the heart of this system, called Hi-ONE, is a critical enabler. Each Hi-ONE unit moves 7.2 Tbit/s and carries a built-in light source. By fitting 5,500 of these units into a single pod, Huawei eliminates the need for 48,000 traditional 800G pluggable optical modules.
The practical benefits of this optical integration are substantial. Huawei reports that the Hi-ONE approach reduces power draw by more than 550 kilowatts and doubles the system’s fault-free operating time, lifting availability to 99.8%. The company has submitted an implementation agreement on this near-packaged optics technology to the Optical Internetworking Forum, signaling its intention to establish industry standards around its approach.
Huawei also upgraded its TaiShan 950 SuperPoD for larger-scale AI workloads, supporting up to 4,096 nodes and a unified memory pool. The OceanStor M900 storage cluster completes the infrastructure picture, together forming the basis of systems targeting up to one million NPUs.
UnifiedBus: The Interconnect Backbone for Million-Processor Systems
Underlying Huawei’s entire AI infrastructure strategy is UnifiedBus, a new interconnect architecture designed to wire massive numbers of processors into a single, coherent computing system. The ambition is extraordinary: Huawei envisions UnifiedBus eventually connecting one million processors into what would effectively be the world’s largest single computer. This vision reflects a fundamental belief that the future of AI computing lies not in individual chip performance but in the ability to aggregate enormous numbers of processors into seamlessly coordinated systems.
The UnifiedBus architecture underpins an 11-chip portfolio that Huawei has developed around its Ascend processors. This comprehensive approach to interconnect technology ensures that as the Ascend series evolves, the systems built around them can scale accordingly, multiplying the effective computing power available for the most demanding AI workloads.
Manufacturing Constraints and the SMIC Partnership
The technical achievements outlined in Huawei’s roadmap must be understood within the context of the severe manufacturing constraints the company faces. SMIC, Huawei’s primary domestic foundry partner, remains stuck at 7-nanometer process technology due to U.S. and allied export controls that restrict access to advanced extreme ultraviolet lithography equipment. The 7nm node has been used to manufacture Huawei’s Ascend series of AI accelerators, creating a fundamental ceiling on the performance that can be achieved through traditional scaling.
SMIC has made progress with its N+3 node, a 5nm-class process that represents a full generation ahead of the older N+2 technology. However, this advance comes with significant challenges. TechInsights analysis confirms that the N+3 node, despite achieving impressive DUV multi-patterning implementation, encounters substantial yield challenges, particularly due to aggressively scaled metal pitch. The Huawei Kirin 9030 SoC produced on this node is likely manufactured at an operating loss, with a significant portion of dies being discarded or used for downgraded chips.
These manufacturing realities explain Huawei’s strategic emphasis on system-level innovation and architectural efficiency. If the company cannot match Nvidia’s per-chip performance due to process technology limitations, it can attempt to compensate through superior system design, larger scale, and more efficient interconnect.
Production Scaling: From 910C to the Next Generation
Huawei’s current production capabilities provide the foundation for its ambitious roadmap. The company plans to produce approximately 600,000 Ascend 910C chips in 2026, roughly double its 2025 output. Overall, Huawei aims to increase its Ascend line’s total die production to as many as 1.6 million units in 2026, up from a maximum of 1 million in 2025.
The successor to the 910C, internally designated the 910D, is expected to debut in late 2026 with an ambitious four-die packaging design. Rather than integrating two dies into a single chipset as with the 910C, the 910D will integrate four dies, significantly increasing computational density per package. Huawei targets production of 100,000 of these new chipset units.
These production targets, if achieved, would represent a major technical breakthrough and would suggest that Huawei and SMIC have found ways to mitigate some of the bottlenecks that have historically constrained their AI business. Chinese enterprises from Alibaba to DeepSeek require millions of AI chips to develop and operate AI services, and Huawei’s ability to supply these chips domestically is critical to China’s broader AI ambitions.
The Software Ecosystem Challenge: CANN vs. CUDA
While hardware specifications capture attention, the true battleground for AI chip dominance extends into software ecosystems. Nvidia’s CUDA platform has enjoyed nearly two decades of development and has become the de facto standard for AI development, with an enormous library of optimized frameworks, tools, and applications. Huawei’s equivalent, the CANN architecture, faces the formidable challenge of persuading enterprises to migrate from CUDA, a transition that carries high engineering costs and significant operational risks.
The software gap represents perhaps the most significant obstacle to Huawei’s ambitions. Even if the company succeeds in delivering competitive hardware, the practical utility of that hardware depends on the availability of software that can effectively harness its capabilities. Huawei has been investing heavily in CANN and related software tools, but closing the ecosystem gap with CUDA will require sustained effort over many years.
The challenge extends beyond individual developers to the broader enterprise IT landscape. Organizations that have built their AI infrastructure around Nvidia’s platform face substantial switching costs, including retraining staff, rewriting code, and validating performance across new hardware. The decision to migrate to Huawei’s platform is therefore not purely technical but also strategic, involving considerations of supply chain security, regulatory compliance, and long-term vendor relationships.
Competitive Positioning: The Performance Gap and Its Implications
The Council on Foreign Relations has offered a sobering assessment of Huawei’s competitive position relative to Nvidia. According to their analysis, the performance gap between U.S. and Chinese AI chips is not only large but growing. The best U.S. AI chips are currently approximately five times more powerful than Huawei’s best offerings, and by 2027, that gap is projected to widen to seventeen times. Perhaps most striking is the observation that, according to Huawei’s own public roadmap, the company’s next-generation chip in 2026 will actually be less powerful than its best chip today, a regression that may indicate SMIC’s difficulties in producing high-performing AI chips at scale.
Huawei’s strategy of compensating for inferior quality with higher quantity is also facing challenges. Even under aggressive assumptions that Huawei will produce 800,000 AI chips in 2025, two million in 2026, and four million in 2027 the company would still produce only about 5 percent of Nvidia’s aggregate AI computing power in 2025, falling to 4 percent in 2026 and 2 percent in 2027. The mathematics of this gap are unforgiving: even a hundredfold increase in AI chip production by 2027 would not bring Huawei to half of Nvidia’s output.
Yet these comparisons, while important, may obscure the genuine progress Huawei has made and the unique value proposition it offers to Chinese customers. The CloudMatrix 384 system, built around 384 Ascend 910C chips, delivers approximately 300 petaflops of compute performance, exceeding the 180 petaflops of Nvidia’s GB200 NVL72 system. While Huawei’s individual chips are underpowered compared to Nvidia’s, the system-level aggregation of hundreds of processors allows CloudMatrix to surpass Nvidia’s flagship offering in aggregate performance, memory capacity, and memory bandwidth.
The trade-off is energy consumption: CloudMatrix 384 consumes approximately 559 kilowatts per hour, around four times the power draw of Nvidia’s equivalent system. For data center operators in China with access to sufficient power, however, this trade-off may be acceptable, particularly given that Nvidia’s most powerful systems are unavailable for purchase due to U.S. export restrictions.
Market Dynamics and the Domestic Replacement Imperative
The broader market context in which Huawei operates has been fundamentally reshaped by U.S. export controls. Nvidia’s market share in China has plummeted from a historical high of approximately 90 percent to around 55 percent, a dramatic shift driven by restrictions on the export of advanced AI chips. Domestic manufacturers, including Huawei, Baidu’s Kunlun, and Alibaba’s T-Head, have capitalized on this vacuum, collectively capturing more than 40 percent of the market.
Government policy has accelerated this transition. Chinese state-owned data centers are now required to procure at least 50 percent of their chips from domestic suppliers, providing a guaranteed market for Huawei and its peers. The Chinese government has also prepared a 295 billion yuan plan to fund AI infrastructure buildout, further stimulating domestic demand.
The future market structure is likely to evolve along two distinct tracks. Government and state-owned enterprise customers will prioritize supply chain security and regulatory compliance, making domestic chips the default choice regardless of performance differentials. Private sector giants, by contrast, will weigh performance advantages against compliance risks, creating a more nuanced competitive dynamic.
The Ascend 910C and 910D: Current Generation and Successor
The Ascend 910C, launched in the first quarter of 2025, remains Huawei’s flagship AI accelerator in production. Research from DeepSeek indicates that the 910C delivers approximately 60 percent of the performance of Nvidia’s prior-generation H100 in inference workloads. While this represents a significant gap, it also demonstrates meaningful progress from previous generations and provides a capable platform for many AI inference applications.
The 910D, expected in late 2026, will push the boundaries of what Huawei can achieve with its available manufacturing technology. The four-die packaging design represents a significant engineering challenge, requiring advanced packaging techniques to integrate multiple chiplets into a single coherent processor. If successful, the 910D will improve computational density and cost-effectiveness, allowing Huawei to deliver more AI processing power per unit area and per dollar of manufacturing cost.
CloudMatrix and the SuperNode Architecture
Huawei’s CloudMatrix 384 system, showcased at the World Artificial Intelligence Conference in Shanghai, represents the company’s most direct challenge to Nvidia’s rack-scale AI server offerings. The system uses 384 Ascend 910C chips distributed across 16 racks 12 for compute and four for networking components. By stacking hundreds of chips with high-speed interconnects, Huawei achieves aggregate performance that surpasses Nvidia’s GB200 NVL72 despite using individually less capable processors.
The SuperNode architecture at the heart of CloudMatrix enables chips to interconnect at extremely high speeds, effectively transforming hundreds of individual processors into a single, massively parallel computing resource. This architectural approach reflects a fundamental insight: for many AI workloads, aggregate system performance matters more than individual chip performance. By prioritizing interconnect bandwidth and system-level efficiency, Huawei can deliver competitive system-level performance using chips that are individually less advanced.
Huawei plans to extend this approach with the Atlas 950 and Atlas 960 SuperNodes, designed to support 8,192 and 15,488 Ascend chips respectively. These systems would represent an unprecedented scale of AI computing aggregation, potentially enabling AI training runs that would be impossible on smaller systems.
HBM and the Memory Bottleneck
High-bandwidth memory represents a critical bottleneck in AI chip development. HBM provides the massive memory bandwidth required to feed data-hungry AI processors, and access to advanced HBM has been a significant constraint for Chinese chipmakers, historically limited to South Korean and U.S. suppliers.
Huawei’s development of proprietary HBM technology represents a significant breakthrough. The Ascend 950 chip is powered by the company’s own HBM, overcoming a key bottleneck that China has faced. This self-sufficiency in memory technology is essential for Huawei’s long-term roadmap, as it removes a critical dependency that could otherwise be exploited by export controls.
The progression of HBM specifications across the Ascend roadmap from 288 GB at 9.6 TB/s in the 960 series to 384 GB at 38.4 TB/s in the 980 demonstrates Huawei’s commitment to closing the memory bandwidth gap with international competitors. These are ambitious targets that will require sustained investment in memory technology research and manufacturing capacity.
Implications for the Global AI Infrastructure Landscape
Huawei’s accelerated AI chip roadmap has profound implications for the global AI infrastructure landscape. For China, it represents a path toward greater self-sufficiency in AI computing, reducing vulnerability to export controls and supply chain disruptions. For the global market, it introduces a viable alternative to Nvidia’s dominance, potentially leading to a more multipolar AI chip ecosystem.
The strategic response of the United States and its allies will be critical in shaping this landscape. The Council on Foreign Relations argues that Huawei is not a threat that justifies loosening export controls but rather evidence that the controls are working. This perspective suggests that maintaining and potentially tightening restrictions on advanced chip exports to China remains the preferred policy approach.
Yet the long-term effectiveness of export controls depends on Huawei’s continued inability to close the performance gap. If Huawei’s accelerated roadmap, system-level innovations, and domestic supply chain investments succeed in delivering competitive AI infrastructure, the strategic calculus may shift. The company’s progress in developing proprietary HBM, advanced packaging techniques, and efficient interconnect technologies suggests that it is pursuing a comprehensive strategy to overcome its manufacturing limitations.
Conclusion: A Defining Moment in the AI Chip Race
Huawei’s decision to accelerate its AI chip roadmap and publicly disclose its plans represents a defining moment in the global AI semiconductor competition. The company is betting that system-level innovation, architectural efficiency, and domestic supply chain development can compensate for its disadvantages in advanced manufacturing. The Ascend 960’s early arrival, the Atlas 960E SuperPoD’s optical interconnect breakthroughs, and the ambitious targets for the 970 and 980 chips all signal that Huawei intends to remain a serious competitor in the AI infrastructure market.
The challenges, however, are formidable. The performance gap with Nvidia remains large and, according to some analyses, is widening. The software ecosystem gap in CUDA versus CANN is substantial and will take years to close. Manufacturing constraints at SMIC continue to limit what Huawei can achieve with traditional scaling. And the geopolitical environment that produced these constraints shows no signs of easing.
What Huawei has demonstrated is that it possesses the engineering talent, strategic vision, and institutional commitment to pursue an ambitious AI chip roadmap under the most challenging circumstances. Whether that roadmap translates into market success and technological leadership will depend on execution across a broad front: chip design, manufacturing, software development, system integration, and customer adoption. The coming years will reveal whether Huawei’s bet on system-level innovation over per-chip performance proves correct, and whether the company can maintain its accelerated cadence in the face of persistent obstacles.
